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? 2005 fairchild semiconductor corporation ds011995 www.fairchildsemi.com february 1994 revised october 2005 74lcx373 low voltage octal transparent latc h with 5v tolerant inputs and outputs 74lcx373 low voltage octal transparent latch with 5v tolerant inputs and outputs general description the lcx373 consists of eight latches with 3-state outputs for bus organized system applicatio ns. the device is designed for low voltage (3.3v or 2.5v) v cc applications with capability of interfacing to a 5v signal environment. the lcx373 is fabricated with an advanced cmos technology to achieve high speed operation while maintaining cmos low power dissipation. features 5v tolerant inputs and outputs 2.3v?3.6v v cc specifications provided 8.0 ns t pd max (v cc 3.3v), 10 a i cc max power-down high impedance inputs and outputs supports live insertion/withdrawal (note ) 24 ma output drive (v cc 3.0v) implements patented noise/emi reduction circuitry latch-up performance exceeds jedec 78 conditions esd performance: human body model 2000v machine model 200v leadless pb-free dqfn package note 1: to ensure the high-impedance state during power up or down, oe should be tied to v cc through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. ordering code: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. pb-free package per jedec j-std-020b. note 2: dqfn package available in tape and reel only. note 3: ?_nl? indicates pb-free package (per jedec j-std-020b). device available in tape and reel only. order number package package description number 74lcx373wm m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lcx373sj m20d pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lcx373bqx (preliminary) (note 2) mlp020b pb-free 20-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 4.5mm 74lcx373msa msa20 20-lead shrink small outli ne package (ssop), jedec mo-150, 5.3mm wide 74lcx373mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74lcx373mtcx_nl (note 3) mtc20 pb-free 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide
www.fairchildsemi.com 2 74lcx373 logic symbols ieee/iec connection diagrams pin assignments for soic, sop, ssop, tssop pad assignments for dqfn (top view) pin descriptions truth table h high voltage level l low voltage level z high impedance x immaterial o 0 previous o 0 before high-to-low transition of latch enable functional description the lcx373 contains eight d-type latches with 3-state stan- dard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e. a latc h output will change state each time its d input changes. when le is low, the latches store the information that was present on the d inputs a setup time pre- ceding the high-to-low transition of le. the 3-state stan- dard outputs are controlled by the output enable (oe ) input. when oe is low, the standard outputs are in the 2-state mode. when oe is high, the standard outputs are in the high imped- ance mode but this does not interfere with entering new data into the latches. pin names description d 0 ?d 7 data inputs le latch enable input oe output enable input o 0 ?o 7 3-state latch outputs inputs outputs le oe d n o n xhx z hll l hlh h llx o 0
3 www.fairchildsemi.com 74lcx373 logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays.
www.fairchildsemi.com 4 74lcx373 absolute maximum ratings (note 4) recommended operating conditions (note 6) note 4: the absolute maximum ratings are those values beyond which the sa fety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?rec ommended operating conditions? table will define the conditions for actual device operation. note 5: i o absolute maximum rating must be observed. note 6: unused inputs must be held high or low. they may not float. dc electrical characteristics symbol parameter value conditions units v cc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to 7.0 v v o dc output voltage 0.5 to 7.0 output in 3-state v 0.5 to v cc 0.5 output in high or low state (note 5) i ik dc input diode current 50 v i gnd ma i ok dc output diode current 50 v o gnd ma 50 v o v cc i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature 65 to 150 c symbol parameter min max units v cc supply voltage operating 2.0 3.6 v data retention 1.5 3.6 v i input voltage 05.5v v o output voltage high or low state 0 v cc v 3-state 0 5.5 i oh /i ol output current v cc 3.0v 3.6v 24 ma v cc 2.7v 3.0v 12 v cc 2.3v 2.7v 8 t a free-air operating temperature 40 85 c t/ v input edge rate, v in 0.8v 2.0v, v cc 3.0v 0 10 ns/v symbol parameter conditions v cc t a 40 c to 85 c units (v) min max v ih high level input voltage 2.3 2.7 1.7 v 2.7 3.6 2.0 v il low level input voltage 2.3 2.7 0.7 v 2.7 3.6 0.8 v oh high level output voltage i oh 100 a2.3 3.6 v cc 0.2 v i oh 8 ma 2.3 1.8 i oh 12 ma 2.7 2.2 i oh 18 ma 3.0 2.4 i oh 24 ma 3.0 2.2 v ol low level output voltage i ol 100 a2.3 3.6 0.2 v i ol 8 ma 2.3 0.6 i ol 12 ma 2.7 0.4 i ol 16 ma 3.0 0.4 i ol 24 ma 3.0 0.55 i i input leakage current 0 v i 5.5v 2.3 3.6 5.0 a i oz 3-state output leakage 0 v o 5.5v 2.3 3.6 5.0 a v i v ih or v il i off power-off leakage current v i or v o 5.5v 0 10 a i cc quiescent supply current v i v cc or gnd 2.3 3.6 10 a 3.6v v i , v o 5.5v (note 7) 2.3 3.6 10
5 www.fairchildsemi.com 74lcx373 dc electrical characteristics (continued) note 7: outputs disabled or 3-state only. ac electrical characteristics note 8: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). dynamic switching characteristics capacitance symbol parameter conditions v cc t a 40 c to 85 c units (v) min max i cc increase in i cc per input v ih v cc 0.6v 2.3 3.6 500 a symbol parameter t a 40 c to 85 c, r l 500 units v cc 3.3v 0.3v v cc 2.7v v cc 2.5v 0.2v c l 50pf c l 50pf c l 30pf min max min max min max t phl propagation delay 1.5 8.0 1.5 9.0 1.5 9.6 ns t plh d n to o n 1.5 8.0 1.5 9.0 1.5 9.6 t phl propagation delay 1.5 8.5 1.5 9.5 1.5 10.5 ns t plh le to o n 1.5 8.5 1.5 9.5 1.5 10.5 t pzl output enable time 1.5 8.5 1.5 9.5 1.5 10.5 ns t pzh 1.5 8.5 1.5 9.5 1.5 10.5 t plz output disable time 1.5 7.5 1.5 8.5 1.5 9.0 ns t phz 1.5 7.5 1.5 8.5 1.5 9.0 t s setup time, d n to le 2.5 2.5 4.0 ns t h hold time, d n to le 1.5 1.5 2.0 ns t w le pulse width 3.3 3.3 4.0 ns t oshl output to output skew 1.0 ns t oslh (note 8) 1.0 symbol parameter conditions v cc t a 25 c units (v) typical v olp quiet output dynamic peak v ol c l 50 pf, v ih 3.3v, v il 0v 3.3 0.8 v c l 30pf, v i 2.5v, v il 0v 2.5 0.6 v olv quiet output dynamic valley v ol c l 50 pf, v ih 3.3v, v il 0v 3.3 0.8 v c l 30pf, v i 2.5v, v il 0v 2.5 0.6 symbol parameter conditions typical units c in input capacitance v cc open, v i 0v or v cc 7pf c out output capacitance v cc 3.3v, v i 0v or v cc 8pf c pd power dissipation capacitance v cc 3.3v, v i 0v or v cc , f 10 mhz 25 pf
www.fairchildsemi.com 6 74lcx373 ac loading and waveforms generic for lcx family figure 1. ac test circuit (c l includes probe and jig capacitance) waveform for inverting and non-inverting functions propagation delay. pulse width and t rec waveforms 3-state output low enable and disable times for logic 3-state output high enable and disable times for logic setup time, hold time and recovery time for logic t rise and t fall figure 2. waveforms (input characteristics; f =1mhz, t r = t f = 3ns) test switch t plh , t phl open t pzl , t plz 6v at v cc 3.3 0.3v v cc x 2 at v cc 2.5 0.2v t pzh ,t phz gnd symbol v cc 3.3v 0.3v 2.7v 2.5v 0.2v v mi 1.5v 1.5v v cc /2 v mo 1.5v 1.5v v cc /2 v x v ol 0.3v v ol 0.3v v ol 0.15v v y v oh 0.3v v oh 0.3v v oh 0.15v
7 www.fairchildsemi.com 74lcx373 schematic diagram generic for lcx family
www.fairchildsemi.com 8 74lcx373 tape and reel specification tape format for dqfn tape dimensions inches (millimeters) reel dimensions inches (millimeters) package tape number cavity cover tape designator section cavities status status leader (start end) 125 (typ) empty sealed bqx carrier 3000 filled sealed trailer (hub end) 75 (typ) empty sealed tape sizeabcdnw1w2 12 mm 13.0 0.059 0.512 0.795 2.165 0.488 0.724 (330.0) (1.50) (13.00) (20.20) (55.00) (12.4) (18.4)
9 www.fairchildsemi.com 74lcx373 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
www.fairchildsemi.com 10 74lcx373 physical dimensions inches (millimeters) unles s otherwise noted (continued) pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
11 www.fairchildsemi.com 74lcx373 physical dimensions inches (millimeters) unles s otherwise noted (continued) pb-free 20-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 4.5mm package number mlp020b
www.fairchildsemi.com 12 74lcx373 physical dimensions inches (millimeters) unles s otherwise noted (continued) 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide package number msa20
13 www.fairchildsemi.com 74lcx373 physical dimensions inches (millimeters) unles s otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
www.fairchildsemi.com 14 74lcx373 low voltage octal transparent la tch with 5v tolerant inputs and outputs disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation as used herein: 1. life support devices or s ystems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordanc e with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reason- ably expected to cause the failu re of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specif ications for product develop- ment. specifications may change in any manner without notice. preliminary first production this datasheet contai ns preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet cont ains final specifications . fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been dis- continued by fairchild semiconductor. the datasheet is printed for ref- erence information only.

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